The present application is related to and claims priority from Korean Application No. 2002-44226, filed Jul. 26, 2002, the disclosure of which is incorporated herein as if set forth in its entirety.
The present invention relates to semiconductor devices and methods of fabricating semiconductor devices, more specifically, the present invention relates to interconnection structures for semiconductor devices.
A semiconductor integrated circuit (IC) typically includes electrically isolated elements, such as a transistor formed at a substrate, a contact hole, and an interconnection selectively connecting the otherwise isolated elements. For example, the contact hole and the interconnection may connect a first active region to a second active region, a first gate electrode to a second gate electrode and/or a gate electrode to active region as needed.
FIG. 1A is a cross-sectional view illustrating a conventional interconnection structure. In FIG. 1A, the region A illustrates an interconnection between active regions, the region B illustrates an interconnection between gate electrodes, and the region C illustrates an interconnection of a gate electrode to an active area. Referring to FIG. 1A, in the region A, a field region 6 is disposed in the substrate 2 to define a first active region 16a and a second active region 16b that are doped with impurities. An interlayer dielectric 20 is provided on the substrate 2. Contact plugs 22 that electrically connect to the active regions 16a and 16b are formed through the interlayer dielectric 20. An interconnection line 34 is provided on the interlayer dielectric 20 to electrically connect the contact plugs 22 to each other. Thus, the first active region 16a is connected to the second active region 16b through the contact plugs 22 and the interconnection line 34.
In the region B of FIG. 1A, an active region 16c doped with impurities is provided in the substrate 2 between field areas 6. A first conductive line 10a and a second conductive line 10b are disposed at respective ones of the field areas 6. While the conductive lines 10a and 10b are formed at the field areas 6 in FIG. 1A, the conductive lines 10a and/or 10b may become a gate electrode when crossing over the active region 16c. An interlayer dielectric 20 is provided on the substrate 2 including the conductive lines 10a and 10b. Contact plugs 24 are connected to the conductive lines 10a and 10b through the interlayer dielectric 20. The contact plugs 24 are also connected to each other through the interconnection line 36. Thus, the contact plugs 24 and the interconnection line 36 electrically connect the first conductive line 10a to the second connective line 10b. 
The region C of FIG. 1A illustrates a MOS-transistor having a gate structure and a source/drain region 18 on both sides of the gate structure. The gate structure includes a gate insulator 8, a gate electrode 10c, and spacers 14 on sidewalls of the gate electrode 10c. The source/drain region 18 is provided by a lightly doped region 12 and a heavily doped region 16d. An interlayer dielectric 20 is provided on the substrate 2 having the MOS-transistor. And a contact plug 26 is also formed to electrically connect both the gate electrode 10c of the MOS-transistor and a doped active region 16d through the interlayer dielectric 20. The contact plug 26 is connected to an interconnection line 38.
As mentioned above, conventionally, otherwise electrically isolated regions are electrically connected to each other using contact plugs, such as the contact plugs 22, 24 and 26 and interconnection lines, such as the interconnection lines 34, 36 and 38. The interlayer dielectric 20 is selectively etched to form a contact hole where the contact plugs 22, 24 and 26 will be disposed. Processes for forming a hole pattern to provide contact plugs may become difficult as a semiconductor devices become more highly integrated.
In addition, as the semiconductor device becomes more highly integrated, processes for isolating adjacent patterns may become more difficult. For example, when a misalignment arises in a photolithography process for forming a contact hole on conductive lines 10a and 10b of the region B, an electrical short may occur between the active region 16c doped with impurities and the conductive lines 10a and/or 10b. To overcome this problem, the conductive lines 10a and 10b have been used as an ion implantation mask to provide self-alignment of the active region 16c. Thus, the active region 16c of the region B disposed between the field areas 6 is not doped with impurities if the conductive lines cross the region between the field areas 6. Such a case is illustrated in FIG. 1B. Where the conductive line 10 covers the region between the field areas 6, an unwanted MOS-transistor may be formed that may degrade the performance of the device.
Embodiments of the present invention provide an interconnection structure of a semiconductor device and methods of fabricating an interconnection structure. In particular embodiments of the present invention, a first active region and a second active region are provided in a substrate. A first field region in the substrate is disposed between the first active region and the second active region and an interlayer dielectric is provided on the substrate. A first unitary interconnection structure contacts and electrically connects the first active region and the second active region, the first unitary interconnection structure being disposed in the interlayer dielectric.
In further embodiments of the present invention, the first active region and the second active region have a surface substantially coplanar with a surface of the substrate. In such embodiments, the first unitary interconnection structure has a first surface that is substantially coplanar with the surface of the substrate and a second surface, opposite the first surface, that is substantially coplanar with a surface of the interlayer dielectric opposite the surface of the substrate.
In additional embodiments of the present invention, the interlayer dielectric includes an etch stop layer on the substrate, a first dielectric layer on the etch stop layer and a second dielectric layer on the first dielectric layer opposite the etch stop layer. Furthermore, the first dielectric layer and the second dielectric layer may have different etch rates with respect to each other.
The first unitary interconnection structure may be a material selected from the group including tungsten, aluminum, copper, titanium, titanium nitride and/or tantalum nitride.
In still further embodiments of the present invention, a third active region is provided in the substrate and second and third field areas in the substrate are provided on opposite sides of the third active region. A first conductive line is on the second field area and a second conductive line is on the third field area. A second unitary interconnection structure contacts the first conductive line and the second conductive line and electrically connects the first conductive line to the second conductive line. The second unitary interconnection structure is disposed in the interlayer dielectric. Furthermore, a portion of the interlayer dielectric is disposed on the third active region and in a gap between the first conductive line and the second conductive line.
In particular embodiments of the present invention, the first conductive line and the second conductive line each have a respective first surface opposite the substrate. The respective first surfaces of the first conductive line and the second conductive line are substantially coplanar. The first surfaces of the first conductive line and the second conductive line are not coplanar with the surface of the substrate. The second unitary interconnection structure has a first surface that is substantially coplanar with the first surfaces of the first and second conductive lines and the second unitary interconnection structure has a second surface, opposite the first surface of the second unitary interconnection structure, that is substantially coplanar with a surface of the interlayer dielectric opposite the surface of the substrate. The second surface of the first unitary interconnection structure and the second surface of the second unitary interconnection structure may also be substantially coplanar.
In other embodiments of the present invention, the portion of the interlayer dielectric disposed on the third active region has a first surface opposite the substrate that is substantially coplanar with the first surfaces of the first and second conductive lines and the first surface of the second unitary interconnection structure.
In further embodiments of the present invention, the first unitary interconnection structure and the second unitary interconnection structure are made of the same conductive material.
Additionally, the first and the second conductive lines may extend to cross over the first active region. In such embodiments, the first and the second conductive lines crossing the first active region may provide a gate electrode of pass transistors in an SRAM and the second unitary interconnection structure may be a word line.
In yet additional embodiments of the present invention, a fourth active region is provided in the substrate and a MOS-transistor formed at the fourth active region. A third unitary interconnection structure contacts and electrically connects a gate electrode of the MOS-transistor to the fourth active region. The third unitary interconnection structure is disposed in the interlayer dielectric. In such embodiments, the first conductive line, the second conductive line and the gate electrode may be made of at least one of polysilicon, silicide, and/or tungsten. Additionally, a first surface of the fourth active region may be substantially coplanar with the surface of the substrate and a first surface of the gate electrode opposite the substrate is not substantially coplanar with the surface of the substrate. The third unitary interconnection structure may also have a first surface that is substantially coplanar with the first surface of the fourth active region, a second surface that is substantially coplanar with the first surface of the gate electrode and a third surface, opposite the first surface and the second surface of the third unitary interconnection structure, that is substantially coplanar with a surface of the interlayer dielectric opposite the surface of the substrate. The first, second and third unitary interconnection structures may also be the same material.
Additional embodiments of the present invention provide for fabricating an interconnection structure in a semiconductor device by forming a first active region in a substrate, forming a second active region in the substrate and forming a first field region in the substrate disposed between the first active region and the second active region. An interlayer dielectric is formed on the substrate and a first opening formed in the interlayer dielectric exposing the first active region and the second active region. The first opening is filled with a conductive material to form a first unitary interconnection structure connecting the first active region to the second active region.
In further embodiments of the present invention, a third active region is formed in the substrate and second and third field areas are also formed in the substrate and on opposite sides of the third active region. A first conductive line is formed on the second field area and a second conductive line is formed on the third field area. A second opening exposing first surfaces of the first conductive line and the second conductive line is formed in the interlayer dielectric. However, the interlayer dielectric remains in a gap between the first and the second conductive lines. The second opening is filled with a conductive material to form a second unitary interconnection structure contacting the first conductive line and the second conductive line and electrically connecting the first conductive line to the second conductive line.
The first and second openings may be formed by selectively etching portions of the interlayer dielectric corresponding to the first opening and the second opening until the first surfaces of the first and second conductive lines are exposed so as to form the first opening having a portion of the interlayer dielectric remaining at a bottom of the first opening and so as to form a second opening having a portion of the interlayer dielectric remaining in a gap between the first conductive line and the second conductive line. Then, the portion of the interlayer dielectric corresponding to the first opening is selectively etched so as to remove the portion of the interlayer dielectric remaining at the bottom of the first opening so as to expose the first active region and the second active region at the bottom of the first opening.
Furthermore, forming an interlayer dielectric may be provided by forming a first interlayer dielectric on the substrate and forming a second interlayer dielectric on the first interlayer dielectric. In such a case, the first and second openings may be formed by selectively etching the second interlayer dielectric until a surface of the first interlayer dielectric is exposed to form the first opening and the second opening. Then a portion of the first interlayer dielectric exposed at a bottom of the first opening is selectively etched to reduce a difference between a thickness of the first interlayer dielectric from the substrate to a bottom of the first opening and a thickness of the first interlayer dielectric from the first surfaces of the first and second conductive lines to a bottom of the second opening. Then the first interlayer dielectric remaining at bottoms of the first opening and the second opening is selectively etched using the second interlayer dielectric as an etching mask to expose the first active region and the second active region at a bottom of the first opening and to expose the first conductive line and the second conductive line at a bottom of the second opening, wherein a portion of the first interlayer dielectric remains between the first conductive line and the second conductive line.
Additionally, forming an interlayer dielectric may also include forming an etch stop layer disposed between the first interlayer dielectric and the substrate. In such a case, forming a first opening and forming a second opening includes removing the etch stop layer exposed at a bottom of the first opening and a bottom of the second opening.
Furthermore, filling the first opening and filling the second opening may be carried out simultaneously. The first unitary interconnection structure and the second unitary interconnection structure may also be made tungsten, aluminum, copper, titanium, titanium nitride, and/or tantalum nitride.
In further embodiments of the present invention, a third active region is formed in the substrate and a transistor formed at the third active region and having an electrode having a first surface that is opposite and spaced apart from a surface of the substrate. A second opening is formed in the interlayer dielectric exposing the first surface of the electrode and the third active region. The second opening is filled with a conductive material to form a second unitary interconnection structure contacting the electrode and the third active region and electrically connecting the electrode to the third active region.
In yet other embodiments of the present invention, an interconnection structure for a semiconductor device is provided by forming a first damascene interconnect structure that directly connects at least one of a first active area in a substrate, a first conductive line on the substrate and/or a first electrode on the substrate to at least one of a second active area in the substrate, a second conductive line on the substrate and/or a second electrode on the substrate. Additionally, a second damascene interconnect structure may also be formed that directly connects at least one of the first active area in a substrate, the first conductive line on the substrate and/or the first electrode on the substrate to at least one of the second active area in the substrate, the second conductive line on the substrate and/or the second electrode on the substrate. At least one of the first active area in a substrate, the first conductive line on the substrate and/or the first electrode on the substrate to at least one of the second active area in the substrate, the second conductive line on the substrate and/or the second electrode on the substrate connected by the first damascene interconnect structure are from the at least one of the first active area in a substrate, the first conductive line on the substrate and/or the first electrode on the substrate to at least one of the second active area in the substrate, the second conductive line on the substrate and/or the second electrode on the substrate connected by the second damascene interconnect structure.
Furthermore, the first damascene interconnect structure and the second damascene interconnect structure may be formed simultaneously and/or of the same material.